The present invention relates to a signal detection method, a power consumption control method, a signal detecting device and a power consumption control device that detect input of a signal to an input terminal; a frequency detection method and a frequency detecting device that detect the frequency of the signal; a signal detection method, a power consumption control method, a signal detecting device and a power consumption control device that detect whether a signal inputted to an input terminal is in a first state in which the signal repeatedly goes to a high level and a low level alternately, or in a second state in which the signal is kept at a high level or a low level; and an electronic apparatus comprising the power consumption control device.
In an apparatus for processing a signal inputted from outside, when a signal to be processed is not inputted, the apparatus is not operating, but a bias current or the like continues to flow, and therefore electric power is often wastefully consumed. For example, when no signal is inputted, a pre-scaler used in a PLL (Phase-Locked Loop) or the like is not operating, but a bias current continues to flow.
In order to reduce such wasteful power consumption, the state of the signal is monitored, and when the signal is stopped, a power consumption reduction signal is outputted to block the bias current or the like (see Japanese Patent Application Laid Open No. 2000-224015). For example, with the use of a power consumption control device that outputs a power save signal (power consumption reduction signal) when it detects that no signal is outputted to a pre-scaler from an oscillator, an attempt is made to reduce power consumption by blocking the bias current in the pre-scaler when it is not operating.
FIG. 1 is a circuit diagram showing the essential structure of an electronic apparatus comprising a power consumption control device. A power consumption control device 6 is connected to an output terminal CL of an oscillator 4 which is an operation monitoring target. A clock signal similar to a signal supplied to a pre-scaler, not shown, is outputted from the output terminal CL. In the power consumption control device 6, one of the terminals of a resistor R8 is connected via an input terminal Vin to the output terminal CL of the oscillator 4, and a capacitor C8 is connected between the other terminal of the resistor R8 and a ground terminal VGD. The node of the resistor R8 and capacitor C8 is connected to a non-inverted input terminal of a comparator 2. Moreover, a reference voltage terminal Vrf is connected to an inverted input terminal of the comparator 2, and the output terminal of the comparator 2 is connected to a power save signal output terminal PS through two inverters INV1 and INV2. The power save signal output terminal PS can be connected, for example, to a power supply device (not shown) to stop power supply to the pre-scaler from the power supply device or reduce the supply voltage, or can be connected, for example, to a pre-scaler (not shown) to give an operation stop signal or a standby signal to the pre-scaler.
In the example of FIG. 1, the clock signal outputted from the CL terminal of the oscillator 4 is integrated by the resistor R8 and capacitor C8 and then outputted to the comparator 2, so when the clock signal is inputted and repeatedly going to a high state and a low state alternately, the power save signal goes high. When the clock signal is stopped in a low state, the power save signal goes low. However, when the clock signal is stopped in a high state, the power save signal goes high similarly to the input of the clock signal, and thus there is the problem that power saving cannot be achieved.
As a method of solving this problem, there is a method in which the DC component of the clock signal outputted from the oscillator 4 is cut. FIG. 2 is a circuit diagram showing the essential structure of an electronic apparatus comprising other power consumption control device in which a capacitor C9 is connected between the above-described input terminal Vin and resistor R8 of the power consumption control device 8. Note that the circuit shown in FIG. 2 has the same structure as the circuit of FIG. 1, except for the capacitor C9. In the example shown in FIG. 2, since the DC component of the clock signal inputted to the input terminal Vin of the power consumption control device 8 is cut, even when the clock signal is stopped in a high state, the power save signal is low. However, since there is no path for actively discharging the charge accumulated in the capacitor C8, it will take a long time until the power save signal goes low after the clock signal was stopped in a high state, and consequently there is the problem that power saving cannot be achieved quickly.
Further, in the Japanese Patent Application Laid Open No. 2000-224015, since different circuits are used to detect the clock signal stopped in a high state and the clock signal stopped in a low state, respectively, it is possible to certainly output a power save signal irrespective of the stopped state of the clock signal. However, this technique has the problem that the circuit becomes larger in size.